1. Field of the Invention
The invention relates to a memory redundancy circuit applicable notably to memories made in integrated circuit form.
2. Discussion of the Related Art
There is then a known way, in the memory addressing technique, of replacing a part (column) of a main memory, when it proves to be defective, by a backup memory or redundancy memory.
In a standard way, a main memory is organized in rows and columns. To cope with the defects detected in the rows or columns, provision is made for redundancy rows or redundancy columns respectively.
For example, if a column of the main memory is defective, it is replaced by a redundancy column as follows: the address of the defective column is memorized in a defective address memory; this defective address memory is a memory of the content addressable type, known as a Content Addressable Memory (CAM); whenever an address is applied to the main memory, this address is also applied to the CAM. If the applied address is identical to the memorized address, the redundancy circuit is put into operation and acts to disconnect the defective column and connect, in its place, a redundancy column in a manner that is invisible to the user.
In practice, depending on the organization of the main memory, if a column is defective, it is rather a group of columns containing this defective column that is replaced by a group of redundancy columns: in general, if a group of columns is defined by an address bit of the large-capacity memory, it is this group of columns that will be replaced as a whole. Hereinafter, for purposes of simplification, the description shall be limited to the replacing of a column rather than the replacing of a group of columns.
For a main memory of several megabits, there is provision for the possibility of repairing several defects; there are therefore as many redundancy columns as there are defective columns or rows that are to be repaired. With each redundancy column, there is associated a respective CAM containing the address of a defective column. If it is desired to repair N defective columns, there should be N redundancy columns and N CAMs. Typically, N=36 for a 4-megabit or 16-megabit memory.
If a column of the main memory is designated by an M-bit address (for example M=5), each CAM contains at least M+1 bits: M bits to define the address of a defective column and one enabling bit to indicate that the redundancy circuit corresponding to this CAM must effectively be activated when the defective address is applied to the CAM.
During the testing of a main memory and the detection of defects, it is therefore necessary to appropriately record CAMs so that, during subsequent attempts to use defective parts of the main memory, these CAMs will automatically replace the defective parts of the main memory by the redundancy memory. However, in certain systems, the CAMs are formed by memory cells comprising complementary memory cells. Depending on whether a one or a zero is recorded in such an element, one memory cell or the other of the element has to be programmed. Consequently, all the elements have to be programmed, whether they are used or not. For, when there is no programming, there is a risk that these CAMs will nevertheless wrongly give an information element (a defective address information element). Various means can be envisaged to make it possible to find out if a CAM has to be used or not.
It is possible, for example, to provide for an enabling bit associated with each CAM to indicate whether this CAM is used or not. However, this makes it necessary, during the test, to position these means, in this case the enable bit of each CAM, in the position corresponding to the use or non-use of each CAM. This therefore makes it necessary, all the same, to have an additional testing time when these CAMs are initialized. The aim of the invention is to prevent, in certain cases, the operations for the initialization of the CAMs and, consequently, to reduce this initialization time. Notably, should no defect be detected in a main memory, no CAM has to be used and it is possible to comprehensively process all the CAMs relating to this main memory. To this end, in the invention, there is added an additional memory element which, by its state, gives information about whether or not the state of the CAMs should be considered. It is shown that there is thus an average gain of 3 seconds for the testing of each memory: this is very significant.